Logic circuit connecting input and output signal lines
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United States of America Patent
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-
Mar 27, 1990
Issued Date -
N/A
app pub date -
Dec 2, 1988
filing date -
May 19, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.
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