Importance

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Abstract

A semiconductor memory device includes: a circuit for defining a cycle in response to a clock and a write enable signal and outputting a write control signal under a specific condition; a unit for inverting the clock to an inverted clock; a circuit for generating a write signal in response to the inverted clock when the write control signal is output; and a memory cell array in which a write access of data is carried out based on the write signal. Where a latch circuit is further provided which latches the write data and transmits the write data to the memory cell array in response to the clock or inverted clock and the write signal, an input terminal and an output terminal can be made common by making a latch timing of the write data different from that of the write enable signal, or the number of input terminals can be decreased by inputting the write data in a time sharing mode. This results in a decrease in scale of the whole circuit as a device. Also, by latching the write enable signal at a change in level of the clock and controlling a generation of the write signal or a prohibition of the generation at a reverse change in level thereof based on a control signal, a write operation can be cancelled, when necessary, with respect to a cell even if an address access to the cell is carried out.

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First Claim