Importance

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Abstract

An apparatus for controlling access to a time division multiplexed (TDM) bus includes a frame address register having a plurality of storage registers for storing a plurality of frame addresses designated for use in communicating over said TDM bus. A frame address latch stores a current frame address. A frame comparator, coupled to the frame address register and the frame address latch, compares the designated frame addresses with the current frame address and produces a first signal indicative of the storage register containing a frame address matching the current frame address. A time slot register has a plurality of storage registers for storing a time slot number designated for use in communicating over said TDM bus. A time slot generator generates a current time slot number. A time slot comparator, coupled to the time slot register and the time slot generator compares the designated time slot number with the current time slot number and produces a second signal indicative of the storage register containing a slot number matching the current time slot number. A token generator, coupled to the frame comparator and the time slot comparator receives the first and second signals and generates a token work unique to the first and second signals. A data transfer circuit transfers a data word to or from the TDM bus responsive to the token word.

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First Claim