Decoder with reduced synchronization capture time
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United States of America Patent
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Apr 17, 1990
Grant Date -
N/A
app pub date -
Sep 30, 1988
filing date -
Sep 30, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A decoder is capable of decoding on a maximum likelihood basis coded symbols of requivalently high coding rate which are produced by deleting those code bits which are located at particular positions in a time sequence of convolutional symbols of low coding rate. The decoder includes a serial-to-parallel (SP) converter for converting a serial data sequence from a dummy bit inserter into parallel sequences. The frequency division phase of the SP converter is determined by a second timing signal which the dummy bit inserter produces in synchronism with a dummy bit inserted phase. A code synchronization is established, frequency division phase synchronization is automatically established. This eliminates the need for the repetitive trial for frequency division phase synchronization only and thereby reduces a synchronization capture time.
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