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Abstract

A semiconductor memory device having a redundant structure for segmented word line arrangement is disclosed. The memory device comprises a plurality of memory blocks, each of the memory blocks having a plurality of normal segment word lines in normal rows coupled to normal memory cells and at least one redundant segment word line in a redundant row coupled to redundant memory cells, a normal row decoder circuit selecting one of the normal rows, a redundant row decoder for selecting the redundant row, a block selection circuit selecting one of the memory blocks and a plurality of normal control gates provided for the normal word lines and a plurality redundant control gates. One of the normal control gates is enabled to select the associated normal segment word line by tbe normal decoder circuit and the block selection circuit when the output of the redundant row decoder is not selected, and one of the redundant control gates is enabled to select the associated segment redundant word line when the output of the redundant row decoder is selected.

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First Claim