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Abstract

A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry (1600) for generating a two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi), circuitry (1800) for producing a result signal, and circuitry (1900) for producing a carry-out signal (Ri), the circuitry being constituted by multiplexed logic. The complemented two input bit exclusive-OR signal (Ai.sym.Bi) is produced by inverting the two input bit exclusive-OR signal (Ai.sym.Bi), thereby making it possible to utilize only 15 transistors in the most cut-down version of the circuit. The invention also relates to a circuit (20) having an addition cell (22) calculating the sum of the input bits and a subtraction cell (24) calculating the difference of the input bits. The circuitry (1600) for producing the two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi) are then used in common both by the addition cell (22) and by the subtraction cell (24).

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