Demultiplexer system

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United States of America Patent

PATENT NO 4920535
SERIAL NO

07284395

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A demultiplexing circuit includes a frame synchronization circuit which simultaneously detects the occurrence of a predetermined frame synchronization pattern and the occurrence of a predetermined identification byte within the frame synchronization pattern. Since the pattern and identification bit are detected simultaneously and from the same data, the circuit is simplified and the demultiplexing is performed more quickly and efficiently.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Iguchi, Kazuo Yokohama, JP 19 478
Ohta, Shinji Kawasaki, JP 42 277
Soejima, Tetsuo Tokyo, JP 17 658
Watanabe, Toshiaki Kawasaki, JP 362 4652

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