Importance

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Abstract

An instruction code access control system used in an instruction code prefetched computer system includes at least an instruction buffer for accumulating prefetched instruction codes, and a data path switch for selectively coupling the instruction buffer to a data path through which an instruction code and an operand data are selectively transferred. The system also comprises a fetch counter for counting the number of the instruction codes accumulated in the instruction buffer from the time a discontinuous program control is carried out. There is provided a counter detector for comparing the value of the fetch counter with a predetermined value. An arbiter is provided for determining, on the basis of the output of the counter detector, a priority between an instruction memory access for instruction code prefetching and an operand access caused as the result of an instruction execution. The arbiter operates to control the data path switch in accordance with the result of the determination.

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First Claim