Hardware logic simulator
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United States of America Patent
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May 8, 1990
Grant Date -
N/A
app pub date -
Feb 24, 1988
filing date -
Feb 25, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A hardware logic simulator includes a first memory, having memory locations respectively corresponding to a plurality of signals in a logic circuit to be simulated, for storing data representing states of the plurality of signals, and a second memory having memory locations respectively corresponding to those of the first memory and an address bus common therewith. When the content of a memory location at a given address of the first memory is changed during simulation, data representing the change in state of the corresponding signal is written in a second memory location corresponding to the given address. The content of the second memory is read out at the end of the simulation and the degree of completeness of the simulation is evaluated.
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