Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system
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United States of America Patent
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-
Aug 1, 1989
Grant Date -
N/A
app pub date -
Jun 30, 1988
filing date -
Jun 30, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A computer system having trace arrays and registers that provide error tracing that permits retry of operations in a pipelined, multiprocessing environment after the operations have been allowed to quiesce. The trace arrays in each retry domain include one master trace array. The master arrays store an event trace identification code, a cross reference event trace indentification code, an error flag, and a cross reference bit. The trace arrays provide a record of the events occurring between the occurrence of an error and the completion of quiescence, when retry can be attemped. Error registers are used to record events in which errors occur during quiescence, where trace arrays cannot be implemented.
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