Digital data processor with fault tolerant peripheral bus communications
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United States of America Patent
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May 15, 1990
Issued Date -
N/A
app pub date -
Jul 29, 1987
filing date -
Oct 1, 1981
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.
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