Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells
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United States of America Patent
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May 15, 1990
Grant Date -
N/A
app pub date -
Dec 27, 1988
filing date -
Dec 27, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A timing circuit is described for a single phase clocked memory. A plurality of models duplicating a word line, a bit line, a cell, etc., are used in the timing circuit. The bit line model is scaled down compared to the actual bit line, however, in conjunction with the drive to the bit line (scaled up model of the cell), the signal on the bit line model is greater than the actual signal on the bit line in the array during reading. This simplifies the detection circuitry needed in the timing circuit and provides more accurate control signals.
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