Content addressable memory array with priority encoder

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United States of America Patent

PATENT NO 4928260
SERIAL NO

07193315

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Abstract

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A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED MICRO DEVICES 901 THOMPSON PLACE SUUNNVALE CALIFORNIA A CA CORPNot Provided

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chuang, Patrick T Cupertino, CA 17 523
Wang, Moon-Yee Cupertino, CA 6 175
Yau, Robert L Cupertino, CA 7 276
Yoshida, Hiroshi Santa Clara, CA 860 8854

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