CMOS read-only memory with static operation
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United States of America Patent
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May 22, 1990
Grant Date -
N/A
app pub date -
Sep 16, 1988
filing date -
Oct 20, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A CMOS read-only memory with static operation having at least one individually activatable row (R.sub.n) and a plurality of main columns (C.sub.1, C.sub.2) which cross the rows, each crossing including pull-down cell (N.sub.1) corresponding to a logical '0' or a pull-down cell (N.sub.2) corresponding to a logical '1', the pull down cells controlled the individually activatable row, the main columns leading to the supply voltage through a respective pull-up transistor (P.sub.1, P.sub.2). To each main column, there is an associated auxiliary column (CX.sub.1, CX.sub.2) which is also connected to the supply voltage through a respective pull-up transistor (PX.sub.1, PX.sub.2). The gates of the pull-up transistors of the main columns are connected to a respective auxiliary column, and the gates of the pull-up transistors of the auxiliary columns are connected to a respective main column.
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