Importance

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Abstract

A TTL to CMOS buffer circuit includes a first buffer receiving a TTL input and a second buffer providing a CMOS output. The first buffer has a first power input connected to Vcc, a second power input connected through a resistor to Vcc, and a third power input connected to Vss. The second buffer has a first power input connected to Vcc, a second power input connected through a resistor to Vss, and a third power input connected to Vss. In the first buffer, two PMOS transistors and three NMOS transistors are serially connected by their current electrodes between the second and the third power input, in that sequence; the second power input is connected to the P channel transistor end of the series and the third power input is connected to the N channel end of the series. In the second buffer, two PMOS transistors and one NMOS transistor is serially connected by their current electrodes in that sequence between the first and the second power inputs; the first power input is connected to the P channel transistor end of the series, and the second power input is connected to the N channel end of the series. The first buffer's first power input is connected to the gate of an NMOS transistor in that buffer, and the second buffer's third power input is connected to the gate of a PMOS transistor in that buffer.

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First Claim