Importance

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Abstract

A Bi-CMOS ECL semiconductor memory cell having a read word line, a write word line and a read bit line is disclosed. The cell includes a bistable circuit having complimentary outputs and also includes a first transfer device and a second transfer device, each having a gate electrode and a current path, the gate electrode of one transfer device being coupled to one of the complimentary outputs of the bistable circuit and the gate of the other transfer device being coupled to the other complimentary output, and the two current paths of the two transfer devices being coupled in series between the read word line and a first reference voltage. The cell further includes a bipolar transistor device having a base, a collector and an emitter. The base is coupled between the two current paths of the two transfer devices and one end of the current path formed between the collector and the emitter of the bipolar transistor being coupled to a second reference (high supply) voltage while the other end of that current path is coupled to the read bit line.

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First Claim