Integrated mos high-voltage level-translation circuit, structure and method
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United States of America Patent
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Jun 26, 1990
Grant Date -
N/A
app pub date -
Jan 19, 1988
filing date -
Jan 19, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A high-voltage level translator circuit is disclosed that is suitable for monolithic integration. The level translator circuit comprises serially-connected current sources suitably ratioed so that the gating on of one current source causes a limited voltage rise across the other current source, which is ungated. The circuit is suitable for integration in a junction-isolated monolithic pseudo-complementary CMOS format.
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