Semiconductor integrated circuit chip-to-chip interconnection scheme
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United States of America Patent
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Jun 26, 1990
Grant Date -
N/A
app pub date -
Jul 21, 1988
filing date -
Jul 21, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer.
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