High speed bus with virtual memory data transfer and rerun cycle capability
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United States of America Patent
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Jun 26, 1990
Issued Date -
N/A
app pub date -
Jun 28, 1989
filing date -
Feb 21, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A high speed data transfer bus with virtual memory capability. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. This minimizes the number of lines required to implement the bus and minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Control signals are employed that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.
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