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Abstract

An emulator circuit utilizes an Intel 8031 microprocessor with external address and data buses to emulate an Intel 8051 single chip microcomputer with no external buses by providing external registers into which the contents of the internal 8031 'Port 0' and 'Port 2' registers are output and functionally 'recreated'. An internal emulation mode is generated in the 8031 wherein internal SFR latch contents are output to the port leads during one state and the port drivers are tri-stated to allow in-level reading of the levels of the port leads during another state. The emulator circuit generates a 'Force Ports' pulse that causes the 'recreated' port registers of the external circuitry to 'force' external 'logic' levels onto the 8031' Port 0 and Port 2 leads.

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First Claim