Method and apparatus for predicting an overflow in an integer multiply
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United States of America Patent
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-
Jul 10, 1990
Grant Date -
N/A
app pub date -
Nov 30, 1988
filing date -
Nov 30, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An overflow prediction scheme is provided to operate in parallel with an integer multiply within a computer to predict overflow conditions of the resultant register. The operands to be multiplied are examined to determine the position of the most significant bit. The position values are summed to determine a minimum resultant size. If the minimum resultant size exceeds the size of the data field of the resultant register, an overflow flag is set. If the minimum resultant size is less than the size of the resultant register data field, the overflow flag is not set. When the minimum resultant size equals the size of the resultant register data field, the setting of the overflow flag will depend on the signs of the expected and actual resultant.
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