Enhanced input/output architecture for toroidally-connected distributed-memory parallel computers
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United States of America Patent
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Jul 17, 1990
Grant Date -
N/A
app pub date -
Oct 8, 1987
filing date -
Oct 8, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A toroidally-connected distributed-memory parallel computer having rows of processors, with each processor having an independent memory. The computer includes at least one common I/O channel adapted to be connected to a single row of processors by buffering mechanisms. Each buffering mechanism is associated with one processor of the single row of processors.
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