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Abstract

A processor architecture that permits the realization of any computing function with a regular array of interconnected procssing elements comprising as few as one processing element. The processing element can be as complex as desired. In its minimum form it can be as simple as a NOR gate and switch coupled with some delay elements, with the connectivity and the control signals combining to impart the flexiblity. In use, an algorithm to be implemented is conceptually mapped onto an array of processing elements arranged in rows and columns, where the data dependencies in the columns are unidirectional, and the data dependencies in the rows of processing elements are at most unidirectional. One or more actual processing elements are conceptually scanned over the array through time multiplexed controls to emulate the entire conceptual array and thus perform the algorithm. The scheduling of the processing and communications functions performed by the processing element is dictated by the conceptual array layout of the algorithm.

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First Claim