Sensitive thyristor with integrated gate-cathode decoupling
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United States of America Patent
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Aug 14, 1990
Issued Date -
N/A
app pub date -
Oct 7, 1988
filing date -
Aug 6, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
So as to avoid untimely triggering of a sensitive thyristor, it is given the structure shown in the accompanying figure, with a passivated furrow SP3 which divides the gate layer P1 into two completely separate zones (zone B and zone C). Zone B comprises on the one hand the whole of the cathode region N1 and on the other a first surface portion P'1 of the P layer adjacent the furrow SP3. Zone C comprises on the one hand an auxiliary N type surface region N3 and on the other a second surface portion P'1 of the layer P1. The cathode metallization CME1 covers the cathode region N1 without covering the region P'1. The gate metallization MG covers at least partially the region P'1. An auxiliary metallization MA separate from the others covers the region P'1 and the region N3.
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