Importance

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Abstract

A multi-chip integrated circuit package includes a high-precision self-aligning assembly including a wafer with alignment apertures, a die with alignment slots and pin blocks for mating with both the apertures and the slots. The apertures, slots and pin blocks can be formed with walls along the <111> crystallographic plane so as to be oblique with respect to the <100> crystallographic planes defining the major wafer and die surfaces. These walls are defined photo-lithographically and formed using a highly anisotropic EDP etch. Electrical interfacing between die and wafer is provided using mating gold bumps and pads. The gold pads are formed on flexible silicon dioxide membranes. The membranes are formed over cavities which can be formed just as the apertures are formed. A second wafer with a silicon dioxide layer is bonded to the wafer with the cavities. Etching away the silicon substrate of the second wafer leaves a silicon dioxide membrane over the cavities. Alternatively, space under silicon dioxide membranes is etched using an EPD etch through L-shaped apertures extending into the silicon substrate. The flexiblity of the membrane provides for good electrical contact despite minor spacing variations between die and wafer. The flip-chip assembly comprising the wafer, die and pin blocks can be held together initially by nickel foil and then mounted in a ceramic housing. A heat sink bolted to the housing provides the pressure required for the gold bumps to securely contact the gold pads and deflect the membranes.

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First Claim