Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
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United States of America Patent
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Aug 28, 1990
Grant Date -
N/A
app pub date -
Feb 6, 1986
filing date -
Feb 6, 1986
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.
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