Cache memory address modifier for dynamic alteration of cache block fetch sequence
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United States of America Patent
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Aug 28, 1990
Grant Date -
N/A
app pub date -
Mar 24, 1988
filing date -
Mar 24, 1988
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Expired
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Abstract
A cache memory includes an address modification circuit for operation during a cache block fetch sequence. The address modification circuit is connected to a polling circuit which receives a first word address from other portions of the cache memory connected to an instruction unit. The polling circuit tests whether a memory module storing the first word is free to make a data return transfer to the cache memory. When the memory module indicates that it is inhibited from making the data return to the cache memory, the address modification circuit selects in order of priority the next word in a cache block to be fetched and polls a memory module storing the next word. Word address selection and polling continues until a free memory module responds or until all words in the cache block have been fetched from main memory.
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Patent Owner(s)
- SUN MICROSYSTEMS, INC.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Beard, Douglas R | Eau Claire, WI | 22 | 1002 |
Ward, William P | Poway, CA | 12 | 355 |
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