Importance

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Abstract

An address counter (2) counts the clock pulses sequentially to provide a count value as an address signal to a coincidence detecting circuit (3) and decoder (4). The coincidence detecting circuit (3) compares delay data applied from a delay data generating circuit (8) with the address signal and applies a reset signal to the address counter (2) when they coincide with each other. The address counter (2) repeats sequentially the above-mentioned operation in response to the reset signal after the count of address is reset to a predetermined value. The decoder (4) specifies a memory cell comprised in a memory device for performing a reading and writing operation in response to the address signal. The data output circuit (6) and the data input circuit (5) perform the reading and writing operation sequentially to the specified memory cell in response to the control signal outputted from the control circuit (7). As a result, the input data previously written is read and outputted with a delay. Therefore, a delayed input data can be obtained as an output data.

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First Claim