Importance

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Abstract

A switch system for circuit and/or packet-switched communications comprising a central controller; a clock signal source; a pair of serial memories and a series of consecutive access units each of which being linked on the one hand with an associated subscriber terminal and on the other with the read and write terminal of an associated memory location of the first as well as the second serial memory, the input and the output of the two serial memories being linked with the central controller and the information stored at the memory locations of the first and the second serial memories permitting to be transferred from the first to the last access unit and from the last to the first access unit, respectively, under control of the clock signals, the central controller generating consecutive patterns with always an equal number of time slots, each containing a predetermined number of clock signal periods in which at least an amount of information bits, each having a first or a second binary value, can be written, and each access unit being arranged for rewriting the information bits in a time slot as bits having the same binary value as before they were rewritten or as bits having the second binary value, the locations of the bits that are rewritten as bits having the second binary value being determined by the access unit. For at least a plurality of access units, means are provided for rewriting information bits in a time slot having the second binary value as bits having a first binary value.

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First Claim