Method for making interconnect structures for VLSI devices

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United States of America Patent

PATENT NO 4954214
SERIAL NO

07293789

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Abstract

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In methods for making interconnect structures for semiconductor devices a layer of seed material is formed on a first substantially planar dielectric layer which covers the semiconductor devices at predetermined locations where interconnect conductor is desired, a second substantially planar dielectric insulating layer is formed over the first substantially planar dielectric insulating layer and the seed material, the second layer having openings extending therethrough at the predetermined locations to expose at least a portion of the seed material, and conductive material is selectively deposited on the exposed seed material to fill the openings. The seed material may be a material in the group consisting of aluminum alloys, refractory metals and metal silicides, or may be SiO.sub.2 selectively implanted with silicon ions. The insulating material may be SiO.sub.2. The conductive material used to fill the openings may be tungsten deposited by selective CVD or nickel deposited by selective electroless nickel plating. The steps of the methods may be repeated to form a multilevel interconnect structure. The methods are particularly suited to making interconnect structures for submicron devices.

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Patent Owner(s)

Patent OwnerAddress
STMICROELECTRONICS N V39 CHEMIN DU CHAMP DES FILLES 1228 PLAN-LES-OUATES GENEVA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ho, Vu Quoc Kanata, CA 1 48

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