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Abstract

A digital computer having stored therein a program receives information on pin locations, logic equations and timing delays from a plurality of inputs to a plurality of outputs of a representation of an electronic integrated circuit. A first representation of the electronic integrated circuit is constructed by the program based upon the input information. The first representation has a plurality of nodes interconnecting a plurality of first electronic logic circuit elements, with the first electronic logic circuit elements in the primitives of a first simulator. The first representation is transformed into a second representation which is the logical equivalent of the first representation in accordance with the following rules: All directly serially connected first electronic logic circuit elements that can be collapsed are collapsed; and a first electronic logic circuit element which is not recognized as a primitive by a second simulator is transformed or expanded into equivalent logical elements which are primitives of the second simulator; provided that the second representation does not comprise directly serially connected primitives. The timing delay for each electronic logic circuit element in the second representation is determined. The electronic logic circuit elements in the second representation are converted into a third representation which are in primitives of the second simulator. The third representation is then generated in the syntax of the second simulator.

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First Claim