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Abstract

An integrated telecommunication system for multiple telephone line response and processing having a plurality of interface circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, control communication on a group of telephone line channels connected thereto. Each interface circuit includes a high speed interface microprocessor and a first data storage associated therewith. A first bus system interconnects the plurality of interface processor circuits to signal processor circuits. Each signal processor module includes a cross-point switch and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, a second data storage associated therewith, and one or more of a plurality of telecommunication function circuits controlled thereby. A multi-bus system connects each of the plurality of interface processors to each of the plurality of signal processor circuits and to a main system control processor and a third data storage. The high speed processing requirements of each group of telephone lines is performed by the respective interface control processor and a digital signal microprocessor and main system control processor selectively controls the storage of data in the first, second and third data storages and intercommunication functions between the plurality of interface processor circuits and the plurality of signal processor circuits and the function circuits controlled thereby.

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First Claim