Computer with interface for fast and slow memory circuits
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United States of America Patent
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-
Sep 18, 1990
Issued Date -
N/A
app pub date -
Sep 12, 1989
filing date -
Mar 2, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A CPU with an interface to two different RAMs which operate at different rates. The interface circuit includes a decoder which examines the addresses from the CPU and determines whether a faster cycle or slower cycle is needed. The slow RAM provides video signals to a video display. The fast RAM includes an image of the video signals stored in the first RAM. When the video signals are read by the CPU, they are read only from the fast RAM, however, when it is necessary to update the video signals, they are written into both the slow and fast RAMs.
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