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Abstract

In a content addressable memory, a plurality of equal-sized groups of data bits are accessed simultaneously from a memory and compared with a sequence of groups from an input key code, each group consisting of the same number of consecutive data bits. Each comparison of groups of data bits produces a match indication, and a comparison of groups of data bits is inhibited unless the comparison of the preceding group of memory data bits with the preceding group of key code data bits produced a positive match indication. The match indications are stored in a shift register, which is shifted one step after each comparison to permit or inhibit the next comparison. The memory may be a dynamic semiconductor RAM accessed a row at a time. The data bits from a single row access may be compared in time with the groups of a plurality of groups of data bits, say 4, constituting the entire input key code.

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First Claim