Flexible, programmable cell array interconnected by a programmable switch matrix
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United States of America Patent
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Oct 16, 1990
Issued Date -
N/A
app pub date -
Sep 12, 1988
filing date -
Mar 29, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A high density segmented programmable array logic device utilizes a switch interconnection matrix to couple an array of programmable logic cells. Each programmable logic cell includes programmable input logic macrocells, programmable feedback logic macrocells, programmable output logic macrocells, buried state logic macrocells and an assembly of programmable AND gates and OR gates. Each input macrocell, output macrocell and buried state macrocell has means for generating either a registered/latched output signal or a combinatorial output signal in response to an input signal to the cell. The various switches are used to couple signals to or from the assembly of programmable AND gates and OR gates.
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