Importance

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Abstract

A combined multiple memory array is disclosed which includes at least two differing types of memory arrays located next to and aligned to one another. The individual memory cells of the differing memory arrays are designed wherein the x pitches may vary in order to allow the y pitches to be substantially equal. A common set of row decoders provide common wordline decoding to the differing memory arrays. The memory arrays need not have the same number of words or bits to share the common row decoders. The column decoders may be separate for each array to account for different word sizes. A common set of column decoders is possible with equal word lengths from each array. A significant savings in silicon area may be saved by combining the multiple arrays.

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First Claim