Associative memory having simplified memory cell circuitry
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United States of America Patent
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Oct 23, 1990
Grant Date -
N/A
app pub date -
Jul 17, 1989
filing date -
Jan 13, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.
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