Combinational static CMOS logic circuit
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United States of America Patent
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Nov 6, 1990
Grant Date -
N/A
app pub date -
Aug 3, 1989
filing date -
Aug 3, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.
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