Temperature compensated high speed ECL-to-CMOS logic level translator
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United States of America Patent
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Nov 6, 1990
Grant Date -
N/A
app pub date -
Aug 25, 1989
filing date -
Aug 25, 1989
priority date (Note) -
Expired
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Abstract
An emitter coupled logic (ECL)-to-complementary metal-oxide-semiconductor (CMOS) logic level translator is temperature compensated to track temperature induced shifts in the ECL logic levels. The translator includes a differential amplifier with mid-range reference voltage. A reference voltage generator supplies the reference voltage to the differential amplifier and has a temperature sensitive transistor which changes the value of the circuit output (reference) voltage ambient with temperature shifts.
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