Apparatus and method for burning in integrated circuit wafers
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United States of America Patent
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-
Nov 6, 1990
Grant Date -
N/A
app pub date -
Nov 3, 1989
filing date -
Nov 3, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of burning in integrated circuits on a semiconductor wafer is provided, wherein a burn-in chamber having a flexible membrane probe which is sized so that it can couple to a plurality of contact pads on the semiconductor wafer at one time. The semiconductor wafer is heated to a predetermined burn-in temperature and a bladder which lies behind the membrane probe is inflated so that the membrane probe couples to each of the plurality of contact pads on the wafer. The membrane probe is coupled to an exercise circuit which exercises all of the integrated circuits on the wafer in parallel for a predetermined time.
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