Fully digital phase-locked loop
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United States of America Patent
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-
Nov 6, 1990
Grant Date -
N/A
app pub date -
Oct 30, 1987
filing date -
Oct 31, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A fully digital phase-locked loop comprises a sampler (1), an analog-to-digital converter (2), two quadrature demodulators (3 and 4) and their associated filters (5 and 6), and a decision logic (7) effecting the correction of the sampling phase around the value of the free-running frequency (f.sub.e) by the addition or subtraction of machine cycles of a signal processor (9).
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