Programmable memory state machine for providing variable clocking to a multimode memory
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United States of America Patent
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Nov 13, 1990
Grant Date -
N/A
app pub date -
Sep 26, 1989
filing date -
Sep 26, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A circuit for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse, the circuit comprising apparatus for providing signals indicating a mode of operation for access to a matrix of memory elements, apparatus responsive to the signals provided by the apparatus for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, and apparatus responsive to the signals provided by the apparatus for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate.
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