Programmable configurable logic memory
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United States of America Patent
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-
Nov 20, 1990
Grant Date -
N/A
app pub date -
Sep 22, 1989
filing date -
Sep 22, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A reprogrammable logic array is characterized by the use of a RAM fuse to selectively control the transfer of variable from input lines to intersecting output combination lines of the array. The configuration of the combiner array is programmed by writing to all of the RAM locations that are associated with the array. If a connection is to be made, a logical '1' is written to the RAM cell for that connection and if no connection is desired, a '0' is written to the RAM cell. The array which includes a novel input interface, can be quickly and easily reprogrammed simply by writing to the appropriate RAM cells. The RAM fuses may function as standard static RAM if the device does not need to function as a combiner.
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