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Abstract

A multiplexing parallel analog digital converter including two multiplexers, comparators, a demultiplexer, and a control unit. One multiplexer is provided the reference voltages resulting from a voltage division of inner resistors by a most significant bit reference ladder and a least significant bit reference ladder for the reference voltage of the next comparison. The other multiplexer is provided the reference voltages by accepting an analog input signal and the difference signal between an analog input signal and the output of a 4-bit digital analog converter. By using two multiplexers, only one analog digital converter is needed in this present device, so, the number of comparators is reduced. The multiplexer sends the digital signals compared with the most significant bit signal and the least significant bit signal, respectively, to a most significant output latch and a least significant output latch, respectively, so the 8-bit digital signal is obtained. The control unit is a logic circuit composed of flip-flops and gates, and provides clock signals for the sequential operation of the circuits, such as the operations of the multiplexers.

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First Claim