Generalized digital multiplier and digital filter using said multiplier
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United States of America Patent
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-
Nov 27, 1990
Grant Date -
N/A
app pub date -
Jan 24, 1989
filing date -
Feb 2, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The multiplier according to the invention comprises N shift registers (RD.sub.O, . . . , RD.sub.N-1) containing the words x.sub.i on B bits, N conditional adders (AdC.sub.O, . . . , AdC.sub.N-1) each adding to the partial sum which they receive a constant coefficient (a.sub.1), conditional on the value of the bit (x.sub.i,j) which they receive from the associated register (RD.sub.1) and an adder accumulator (AdAc). The digital filter using such a multiplier also comprises a parallel word input register.
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