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Abstract

An architecture for the input/output circuits and pads of a gate array integrated circuit product functionally configured during the formation and connection of one or more metallization layers. In a preferable practice of the invention, cells of first impurity type and second impurity type transistors are formed in respective parallel but spaced apart rows along the chip perimeters with a pad definition region lying therebetween. Successively adjacent cell transistors are contiguous as to source regions and are electrically separable by cell gate isolation. Preferably, the individual cell transistors have annular gate electrodes with centrally disposed and also fully isolatable drain regions. The input/output architecture of the present invention provides the gate array designer with the ability to selectively define pad size and spacing, to selectively utilize cells for I/O circuit functions, and to selectively isolate and cascade interconnect cell transistors to provide extended ranges of current drive and operating voltage.

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First Claim