Fabrication method of bipolar transistor
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United States of America Patent
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Dec 18, 1990
Grant Date -
N/A
app pub date -
Sep 26, 1988
filing date -
Sep 26, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor. The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current. Also, this polycrystalline silicon is used for the ion implanting mask for the extrinsic base of the NPN transistor and for the emitter, collector of the lateral PNP transistor simultaneously. Therefore, the extrinisc base of NPN transistor and the emitter, collector of the lateral PNP transistor are self-aligned by the polycrystalline silicon, and so one mask is saved by this method.
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