Semiconductor logic device having two-dimensional logic arrays and logic cell chains alternately arranged
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United States of America Patent
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Jan 1, 1991
Grant Date -
N/A
app pub date -
Apr 26, 1989
filing date -
Apr 27, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor logic device having arrays of logic elements and chains of logic cells alternately arranged in a direction substantially perpendicular to the direction of the chains of logic cells in a surface portion of a semiconductor substrate. Each of the logic element arrays has input and output leads extending from the array in the above-mentioned direction substantially perpendicular to the direction of the chains of logic cells so that each of said logic cell chains is in an electrical connection with two adjacent logic element arrays via the input and output leads.
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