Importance

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Abstract

An extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit; an extension module including at least a second peripheral control unit connected to an extended bus; a connection bus interconnecting the base bus of the base module and the extended bus of the extension module; a direct memory access control unit provided for at least one of the base module and the extension module for directly controlling data transfer between the first and second peripheral control units and the memory unit; a first master clock generator unit for supplying first master clocks to the direct memory access control unit and controlling the direct memory access control unit, the first master clocks having a first frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the first peripheral control unit and the memory unit; and a second master clock generator unit for supplying second master clocks to the direct memory access control unit and controlling the direct memory access control unit, the second master clocks having a second frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the second peripheral control unit and the memory unit.

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First Claim