Importance

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Abstract

A system (100, 50, 300) for recovering a clock signal from a serial data signal (102) having rising (204) and falling (206) transitions. The transistions (204, 206) are detected by a transition detector (11, 12, 108, 110) which generates a transition signal (13a, 13b, 109, 111) having a first logic state when a rising (204) or falling (206) transition is detected. The system (100, 50, 300) includes a delay device (22, 120, 122) which delays the transition signal (13a, 13b, 109, 111) by a preselected time period and a gating device (24, 124, 126) responsive to the transition signal (13a, 13b, 109, 111). The gating device (24, 124, 126) is enabled by the transition signal (13a, 13b, 109, 111) when the signal is the first logic state, thereby permitting a system generated clock signal (148) to propagate to a phase comparison system (132, 134, 176, 178, G 1, G4) for comparison with the delayed transition signal (23, 128, 130). The phase comparison system (132, 134, 178, G1, G4) generate a correction signal (30) indicative of the phase difference between the compared signals (23, 25, 144, 152, 130, 154) such that the transitions in clock signal (148) generated are in synchronization with the data transitions (204, 206).

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First Claim